GB9144 Ethernet switching chip

date:2026-07-08 / popularity: / source:

Overview
  • GB9144 is an independently developed high-performance, high-connectivity Ethernet switching chip. It delivers a total switching bandwidth up to 28.8 Tbit/s and supports up to 144×200GE or 72×400GE switching ports.
  • The chip architecture provides a complete set of L2/L3/L4 network protocols as well as features for data centers and metropolitan Ethernet. It complies with the IEEE 802.3 200G/400G Ethernet standard, with ports configurable to 100GE/200GE/400GE flexibly. The chip is designed for building scalable, cost-effective TOR switches, aggregation switches and core switches.

Features
  • Support high-performance switching based on standard Ethernet protocols, with throughput up to 28.8 Tbit/s.
  • Equipped with 144/72 full-duplex high-speed ports, enabling data switching between any two ports.
  • Support X2/X4 network interfaces; each port consists of 2 or 4 lanes of 112 Gbps SerDes, with port transmission rate up to 200 Gbps or 400 Gbps.
  • Support Link-to-Link Rolling CRC check and retransmission.
  • Support automatic link status detection and self-recovery.
  • Support automatic detection and transmission for 1 to 4 SerDes lanes.
  • Support full-rate and half-rate transmission of SerDes lanes.
  • Support IEEE 1149.1 JTAG and IEEE Std 1149.6.
  • Support I2C interfaces at 100 kHz and 400 kHz for internal register read and write access.
  • Support SPI interfaces at 12.5 MHz and 25 MHz to access FLASH for power-on configuration.

Functional Applications
  • Port Specifications
- Port Types: Support a total of 144×200G ports or 72×400G ports
- Port Modes: Support 400GBASE-KR4/CR4, 200GBASE-KR2/CR2
- Management Interfaces: Support dual I2C buses
  • Forwarding Features
- Port Capabilities
√ Support configuration of 400G/200G port rates
√ Support port-level Pause flow control and PFC flow control (8 queues per port)
√ Support two industrial standard FEC algorithms: RS (528,514) for 200G ports and RS (544,514) for 400G ports
√ Support port meter function
√ Support MIB transmit and receive statistics
- L2 Bridging
√ Support IVL/SVL modes
√ Support hardware-based MAC address learning, aging, migration and limit control
√ Support MAC address blacklist
√ Support static MAC addresses
- VLAN
√ Support QinQ
√ Support Access/Trunk/Hybrid interfaces
√ Support bidirectional VLAN filtering
√ Support bidirectional inner and outer VLAN tag editing
√ Support VLAN classification based on MAC address, port, protocol and subnet
√ Support Private VLAN
√ Support VLAN packet transmit and receive statistics
√ Support Spanning Tree Protocols (STP/RSTP/MSTP)
- Link Aggregation
√ Support static and dynamic link aggregation
√ Support multiple hash algorithms
√  Support fault recovery for link aggregation groups
- L2 Multicast
√ Support IGMP packet processing based on VLAN
√ Support multicast packet filtering by VLAN and egress interface
√ Support Layer 2 multicast forwarding to physical ports
- L3 Routing
√ Support VRF
√ Support hardware pre-processing for ARP/ICMP/DHCP and other protocols
√ Support IPv4/IPv6 host routes
√ Support IPv4/IPv6 LPM routes
√ Support URPF
√ Support ECMP
√ Support PBR
- IP Multicast Routing
√ Support multicast entries (S,G) and (*,G)
√ Support RPF
√ Support traffic replication to physical interfaces and logical interfaces
√ Support two processing modes for unknown multicast packets: discard or upload to CPU
- IP Tunnels
√ Support static IPinIP tunnels
√ Support 6to4, ISATAP, GRE and UDP tunnels
  • Security Features
- Support 802.1X authentication based on port and MAC address
- Support port isolation
- Support multi-field matching bonding based on IP/MAC/Port/VLAN
- Support blacklist filtering based on source MAC and source IP addresses
- Support defense against multiple types of DDoS attacks
  • CPU Traffic Protection
- Support rate limiting by traffic group
- Support rate limiting by protocol type
- Support SP/WDRR/RR scheduling mechanisms
- Support overall traffic rate limiting for CPU
- Support rate limiting in bps and pps
  • ACL
- Support bidirectional deployment on physical interfaces and logical interfaces
- Support deep packet parsing
- Support parsing of user-defined field (UDF) packets
- Support matching of L2-L4 header fields
- Support multiple configurable traffic policies
  • Traffic Control & Supervision
- Support storm control
- Support QoS policing
- Support traffic shaping and scheduling
- Support In-band Network Telemetry (INT)
- Support port mirroring
· Data Center Features
- Support VXLAN
- Support NVGRE
- Support ETS
- Support VEPA
  • Stacking
- Support star, chain and ring stacking topologies
- Support aggregation of stacking ports
- Support mirroring on stacking ports
  • SDN Features
- Support OpenFlow V1.3
- Support multi-level flow tables
  • Programmable Pipeline Features
- Support user-defined packet header parsing
- Support matching with user-defined packet header fields
- Support hash lookup
- Support multiple user-defined traffic policies
- Support user-defined statistic counters
- Support user-defined packet header editing
- Support multi-stage instruction tables
- Support multiple arithmetic operation instructions
- Support multiple packet editing instructions
  • Metro Ethernet Features
- Support IEEE 1588 precision clock synchronization
- Support Ethernet OAM
- Support MPLS OAM
- Support ITU-T Y.1731 OAM for Ethernet and MPLS-TP
- Support Ethernet BFD, MPLS BFD and MPLS-TP BFD
 

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